Windows and southbridge platform controller hub interactions

Would anyone know what sort of interactions (communications) takes place between Windows (ANY versions) and the Southbridge (SB) or Platform Controller Hub (PCH) chipset found on most motherboards ? I do know that Windows and the SB or PCH communications involve data to and from IO devices like the hard drive, usb flash drive, network card, audio, keyboard, etc. but what about other communications for example between Windows and a text editor such as Notepad ? ignore the users keystrokes which obviously originates from the keyboard then from the Southbridge or PCH chipset to the application via Southbridge or PCH to Northbridge data bus.

Does the SB or PCH play any other role or have other functions other then to transfer IO data to and from the OS and then from the OS to an application ? Do ALL user mode application communications from the OS come from the Northbridge chipset and NOT through the Southbridge chipset ?

Would there be any online resources a good book which gets in the details of the functioning of the SB or PCH chipset found on computer motherboards ?

Best Regards

xxxxx@hotmail.com wrote:

Would anyone know what sort of interactions (communications) takes place between Windows (ANY versions) and the Southbridge (SB) or Platform Controller Hub (PCH) chipset found on most motherboards ? I do know that Windows and the SB or PCH communications involve data to and from IO devices like the hard drive, usb flash drive, network card, audio, keyboard, etc. but what about other communications for example between Windows and a text editor such as Notepad ?

You are mixing concepts here. Notepad is not hardware, Notepad is an
application. There is no “communication”, in the hardware sense. It’s
all just changing memory locations and executing instructions.

Does the SB or PCH play any other role or have other functions other then to transfer IO data to and from the OS and then from the OS to an application ? Do ALL user mode application communications from the OS come from the Northbridge chipset and NOT through the Southbridge chipset ?

No. The chipsets are not involved. When Notepad needs operating system
services, it just makes a function call. In hardware terms, the
processor just starts readikng instructions from a different spot in memory.

Would there be any online resources a good book which gets in the details of the functioning of the SB or PCH chipset found on computer motherboards ?

There are specs from the chipset makers, of course, but you have some
architectural confusion to clear up before you go into that level of detail.


Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.

Tim a grand thanks so much. I do have a couple of questions to ask of you. When a user plugs in a USB flash drive in a computer does the Southbridge/Platform Controller Hub send initial notification and the data to the OS by way of the Northbridge chipset then to the CPU which notifies the OS yes ? I did take a look at the datasheet for an Intel Southbridge/Platform Controller Hub chipset and there were no instruction set or interface which a developer or Windows could use in order to interface with it at least I could not see. So that would mean in order for the OS to interface with a IO device (USB/Audio/HDD) it would have to be via the instruction set of the CPU which should have certain instructions in order to communicate with the IO device via the Northbridge and then onto the Southbridge chipset yes ?

One last thing could you correct the following excerpts from the following website http://www.wisegeek.com/what-is-the-difference-between-a-chipset-and-a-cpu.htm

“The information, entered through the keyboard, would travel through the Southbridge section of the chipset to the Northbridge section and into the CPU. The CPU would figure out the answer and send it to the program via the Southbridge and then to the graphics system, so it may be displayed on the screen, via the Northbridge. This is a very basic example, but it serves to illustrate the separation of the two components”

Reading the above excerpt why then would the CPU send it to the program via the Southbridge chipset ? Have I missed anything but why would the CPU not notify the OS of the data waiting for the application without having to go through the Southbridge or Platform Controller Hub ? The OS would then notify the application of the pending keyboard entry.

Usually, SB contains the following:

  • USB host controller
  • SATA host controller
  • LPC bridge

On the other side of LPC bridge, there is SuperIo chip (usually separate chip), which does:

  • legacy keyboard and mouse
  • legacy COM/LPT
  • legacy floppy

For software, the internal proprietary NB -> SB bus is just like PCI, and the LPC bus (SB -> SuperIO) is just like lSA. Actually, LPC is “serial ISA”, so LPC bridge is just like PCI->ISA bridge, and includes the stuff like 8237 ISA DMA (ancient PC “system DMA”) implementation.

Note that modern Intel CPUs have NBs embedded to them.

The vendor’s drivers for SB is usually about the SATA part of it.


Maxim S. Shatskih
Microsoft MVP on File System And Storage
xxxxx@storagecraft.com
http://www.storagecraft.com

wrote in message news:xxxxx@ntdev…
> Would anyone know what sort of interactions (communications) takes place between Windows (ANY versions) and the Southbridge (SB) or Platform Controller Hub (PCH) chipset found on most motherboards ? I do know that Windows and the SB or PCH communications involve data to and from IO devices like the hard drive, usb flash drive, network card, audio, keyboard, etc. but what about other communications for example between Windows and a text editor such as Notepad ? ignore the users keystrokes which obviously originates from the keyboard then from the Southbridge or PCH chipset to the application via Southbridge or PCH to Northbridge data bus.
>
> Does the SB or PCH play any other role or have other functions other then to transfer IO data to and from the OS and then from the OS to an application ? Do ALL user mode application communications from the OS come from the Northbridge chipset and NOT through the Southbridge chipset ?
>
> Would there be any online resources a good book which gets in the details of the functioning of the SB or PCH chipset found on computer motherboards ?
>
> Best Regards
>

Forgot to add: sound is also in the SB

“Maxim S. Shatskih” wrote in message news:xxxxx@ntdev…
Usually, SB contains the following:

- USB host controller
- SATA host controller
- LPC bridge

On the other side of LPC bridge, there is SuperIo chip (usually separate chip), which does:

- legacy keyboard and mouse
- legacy COM/LPT
- legacy floppy

For software, the internal proprietary NB -> SB bus is just like PCI, and the LPC bus (SB -> SuperIO) is just like lSA. Actually, LPC is “serial ISA”, so LPC bridge is just like PCI->ISA bridge, and includes the stuff like 8237 ISA DMA (ancient PC “system DMA”) implementation.

Note that modern Intel CPUs have NBs embedded to them.

The vendor’s drivers for SB is usually about the SATA part of it.


Maxim S. Shatskih
Microsoft MVP on File System And Storage
xxxxx@storagecraft.com
http://www.storagecraft.com

wrote in message news:xxxxx@ntdev…
> Would anyone know what sort of interactions (communications) takes place between Windows (ANY versions) and the Southbridge (SB) or Platform Controller Hub (PCH) chipset found on most motherboards ? I do know that Windows and the SB or PCH communications involve data to and from IO devices like the hard drive, usb flash drive, network card, audio, keyboard, etc. but what about other communications for example between Windows and a text editor such as Notepad ? ignore the users keystrokes which obviously originates from the keyboard then from the Southbridge or PCH chipset to the application via Southbridge or PCH to Northbridge data bus.
>
> Does the SB or PCH play any other role or have other functions other then to transfer IO data to and from the OS and then from the OS to an application ? Do ALL user mode application communications from the OS come from the Northbridge chipset and NOT through the Southbridge chipset ?
>
> Would there be any online resources a good book which gets in the details of the functioning of the SB or PCH chipset found on computer motherboards ?
>
> Best Regards
>

>USB flash drive in a computer does the Southbridge/Platform Controller Hub send initial notification

Yes.

It is a root hub (hardware part of the USB HC) who does this. The root hub sets itself to a state of “new hardware appeared” and generates the PCI interrupt.

And, if this is not the root hub but some downlevel hub, then the USB stack in the OS creates the listening interrupt pipe for non-root-hub USB interrupt messages. When the HW is connected, the hub sends this USB interrupt message up the USB bus, so that the USB stack in the OS senses it and starts the HW enumeration/discovery PnP procedure.

and the data to the OS by way of the Northbridge chipset then to the CPU which notifies the OS

NB is usually:

  • FSB-to-PCIe bridge (root complex)
  • FSB-to-propietary-SB-bus bridge
  • DRAM controller

FSB == Frontside Bus == CPU pinout.

Modern CPUs have NBs embedded to them. So no external FSB.

Interrupts go to IO APIC first, which is probably also in NB (since IO APIC is connected to FSB from its upper side). IO APIC sends an FSB message to Local APIC which is in the CPU chip itself.

On SMP, IO APIC is only 1, while Local APIC is per-core.

With MSIs, there is no IO APIC. Interrupt is sent as message up to the PCIe root, which translates it to FSB message sent directly to the proper Local APIC.

there were no instruction set or interface which a developer or Windows could use in order to
interface with it at least I could not see.

Notepad is like 10 software layers up :slight_smile: for the low-level software, SB is just a collection of several HW devices and their drivers.

to be via the instruction set of the CPU which should have certain instructions in order to >communicate with the IO device via the Northbridge and then onto the Southbridge chipset yes ?

Not only with SB and/or NB, but also with any addressable device, i.e. any device on PCI(e) and LPC.

CPU has special IN and OUT opcodes to execute special bus transactions to access control/status registers of the devices, but modern days there is a move away from this, and the CSRs are usually just memory-mapped.

The OS would then notify the application of the pending keyboard entry.

And the OS does exactly this, using WM_KEYDOWN and WM_CHAR messages.


Maxim S. Shatskih
Microsoft MVP on File System And Storage
xxxxx@storagecraft.com
http://www.storagecraft.com

xxxxx@hotmail.com wrote:

Tim a grand thanks so much. I do have a couple of questions to ask of you. When a user plugs in a USB flash drive in a computer does the Southbridge/Platform Controller Hub send initial notification and the data to the OS by way of the Northbridge chipset then to the CPU which notifies the OS yes ?

You are assigning active roles to the bridges that simply do not exist.
The BIOS configures the bridges during boot, and Windows tweaks that
configuration when it starts. After that, the bridges are very little
more than plumbing. There’s no active communication between Windows and
the bridges. Remember, the processor doesn’t have a separate path to
the bridges. In hardware terms, it’s not aware that bridges exist. The
processor simply has an address and data bus. When a driver wants to
talk to a device on a PCIe bus, it knows the physical address that
device was assigned. The code just does normal memory references to
those addresses, and the bridges pass the memory references back and
forth to the bus, transparently. The processor doesn’t know whether the
address goes to memory, I/O, ISA, PCIe, or VME.

When the user plugs in a USB flash drive, the USB host controller (which
might be on the same piece of silicon as the south bridge) notifies its
driver by firing an interrupt. The driver then creates USB requests to
go find out what the device was. Those USB requests are handled by
writing blocks of memory and putting them into a DMA chain.

Also, I don’t think it’s helpful to think about the CPU notifying the
OS. The CPU is really fairly stupid. It doesn’t think it terms of
abstractions. It just executes a stream instructions. You can say that
the host controller notifies the OS, and the way it does that is by
raising an interrupt, which causes the CPU to change the program counter
so that the OS starts running. The CPU doesn’t really know whether the
new location is in an operating system, or a game, or a driver, or a
virus. It’s just following it’s very basic, low-level instructions.

I did take a look at the datasheet for an Intel Southbridge/Platform Controller Hub chipset and there were no instruction set or interface which a developer or Windows could use in order to interface with it at least I could not see.

Right, because you DON’T interface with it. You configure it at boot
time, then you leave it alone to do its routing.

So that would mean in order for the OS to interface with a IO device (USB/Audio/HDD) it would have to be via the instruction set of the CPU which should have certain instructions in order to communicate with the IO device via the Northbridge and then onto the Southbridge chipset yes ?

Virtually all I/O on x86 systems is done through memory-mapping. There
are no special instructions. To communicate with a device, you write to
addresses in the memory range assigned to that device. The processor
doesn’t know that it’s an I/O device. It just generates memory reads
and memory writes. The bridges, by looking at the address in the
request, route it to memory or to a bus, all transparently. There is no
special action by software or hardware to force a request to one of the
bridges.

The x86 does have the IN and OUT instructions for doing I/O. They are
rarely used any more, because their performance is not good, but to the
CPU those are exactly the same as a memory access. There is an
additional pin that says “this address is a memory address” or “this
address is an I/O space address”.

One last thing could you correct the following excerpts from the following website http://www.wisegeek.com/what-is-the-difference-between-a-chipset-and-a-cpu.htm

“The information, entered through the keyboard, would travel through the Southbridge section of the chipset to the Northbridge section and into the CPU. The CPU would figure out the answer and send it to the program via the Southbridge and then to the graphics system, so it may be displayed on the screen, via the Northbridge. This is a very basic example, but it serves to illustrate the separation of the two components”

Reading the above excerpt why then would the CPU send it to the program via the Southbridge chipset ? Have I missed anything but why would the CPU not notify the OS of the data waiting for the application without having to go through the Southbridge or Platform Controller Hub ? The OS would then notify the application of the pending keyboard entry.

There’s nothing fundamentally wrong with that excerpt, but you are
reading WAY more into this than you really should. One of the key
points you are missing is that all of that signal routing is automatic
and transparent. Yes, a keystroke will travel through the southbridge
and the northbridge into the CPU, but no one has to take any action to
make that happen. The bridges just pass the signals along, based on
their boot-time configuration.

Also, remember that nothing happens on its own. The keyboard can’t
magically force a keystroke to take the path described above. There
might be an interrupt to say that “the keyboard device has something for
you”, but processor has to go read a memory-mapped address to discover
what the key was. That key then gets translated into window messages
and written into memory, where some application will read it later. If
the application decides to display that character on the screen, it
makes an operating system call that eventually writes the data to the
memory addresses assigned to the graphics card. That memory write will
be directed by the northbridge to the graphics chip, but transparently.


Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.