PCI Config address reserved bit layout

Please refer to PCI Conventional Spec 3.0 corrected version at https://www.pcisig.com/members/downloads/specifications/conventional/PCI_LB3.0_CB-2-6-04.pdf.
On page 50 figure 3.2 it says bits 30-24 are reserved and should return always 0. That implies the CfgBaseAdd is always has to be 0x8xxxxxxx. In real world on modern day PCIE platforms the address is never 0x8 but 0xA, 0xE, 0xC etc … that means the reserved bits had valid values and did not return 0. Could someone please point me to the PIC(e) spec where the reserved bits are no longer reserved and have been defined? thanks

xxxxx@gmail.com wrote:

Please refer to PCI Conventional Spec 3.0 corrected version at https://www.pcisig.com/members/downloads/specifications/conventional/PCI_LB3.0_CB-2-6-04.pdf.
On page 50 figure 3.2 it says bits 30-24 are reserved and should return always 0. That implies the CfgBaseAdd is always has to be 0x8xxxxxxx. In real world on modern day PCIE platforms the address is never 0x8 but 0xA, 0xE, 0xC etc … that means the reserved bits had valid values and did not return 0. Could someone please point me to the PIC(e) spec where the reserved bits are no longer reserved and have been defined?

The fact that they are reserved does not mean they are not defined. The
host bridge is required to return 0s for reads of CF8, and should not be
decoding those bits for writes.

Why is this a problem?


Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.

On 24-Nov-2014 19:23, xxxxx@gmail.com wrote:

Please refer to PCI Conventional Spec 3.0 corrected version at https://www.pcisig.com/members/downloads/specifications/conventional/PCI_LB3.0_CB-2-6-04.pdf.
On page 50 figure 3.2 it says bits 30-24 are reserved and should return always 0. That implies the CfgBaseAdd is always has to be 0x8xxxxxxx. In real world on modern day PCIE platforms the address is never 0x8 but 0xA, 0xE, 0xC etc … that means the reserved bits had valid values and did not return 0. Could someone please point me to the PIC(e) spec where the reserved bits are no longer reserved and have been defined? thanks

But PCIe is not PCI. It is a different bus. There some of reserved bits
are utilized.
– pa

I am in Windows. I read the ACPI table to get the PCI Config base address that is the B0D0F0 address. I was expecting 0x8xxxxxxx but get 0xAxxxxxxx which is contrary to the spec. So it is not a problem but question. If the PCICfgBaseAdd always started with a 0x8 then life would become very easy no need to query the ACPI table. But it is not so hence the curiosity. Thanks

Folks,

Yes I realized my misunderstanding,. I was confusing between 0xCfC, 0xCf8 access and memory mapped access. After I re-read the above 2 replies it dawned on me. Thanks a lot this case might be closed