I’m writing device driver for PCIE and it works fine so far, but now we are about to implement another capability n a new pcie card. the new project is about designing and implementing a pcie FPGA-based card which can expose to windows as Serial COM port. for example for an 8 Tx/Rx line(pcie-x8), i want to expose to windows as COM0,COM1,…,COM8.
What is the best way to go about doing this?
In this project I’m a device driver developer, so please guide me in driver point of view.
Many thanks in advance,
The best way to do this is to make these separate functions on PCIe.
Unfortunately, ASIC suppliers such as Altera create a single BAR containing
all eight COM ports. If you do this you need a bus driver, and then a
modified version of the serial port driver (available from the WDK). The
BUS driver will split the BAR into pieces and through a device interface
offer them to the modified serial port driver. The BUS driver will also
own the interrupt, and call the appropriate service routine, that the serial
driver offered through the device interface. Finally the bus driver will
provide the equivalent of KeSynchronizeExecution for the serial ports since
again it owns the interrupt.
I’ve done this project for a number of clients, and license off the shelf
source to them if you device fits the Altera model.
Don Burn
Windows Driver Consulting
Website: http://www.windrvr.com
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Sent: Thursday, April 20, 2017 2:05 AM
To: Windows System Software Devs Interest List
Subject: [ntdev] UART in PCIE card
I’m writing device driver for PCIE and it works fine so far, but now we are
about to implement another capability n a new pcie card. the new project is
about designing and implementing a pcie FPGA-based card which can expose to
windows as Serial COM port. for example for an 8 Tx/Rx line(pcie-x8), i want
to expose to windows as COM0,COM1,…,COM8.
What is the best way to go about doing this?
In this project I’m a device driver developer, so please guide me in driver
point of view.
Many thanks in advance,
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thank you for your general answer. i started to learn about bus driver(i didn’t have any experience on that and it seems quite complicated).
but as much as i find in this documentation we can have multiple BARs in our xilinx-virtex6-FPGA card (page 74)
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwj9parJicLTAhUBPxQKHUzQAiUQFggqMAE&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fuser_guides%2Fv6_pcie_ug517.pdf&usg=AFQjCNHdRFVO5Us8BF48LgHn_qbE3vIn9A&sig2=54Zq4u71pyIPDVy-iOhKmg
what does it mean? does it mean i don’t need bus driver anymore?
thx alot for your help
Take a look at
https://msdn.microsoft.com/windows/hardware/drivers/multifunction/index
Don Burn
Windows Driver Consulting
Website: http://www.windrvr.com
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From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of
xxxxx@yahoo.com
Sent: Wednesday, April 26, 2017 8:08 AM
To: Windows System Software Devs Interest List
Subject: RE:[ntdev] UART in PCIE card
thank you for your general answer. i started to learn about bus driver(i
didn’t have any experience on that and it seems quite complicated).
but as much as i find in this documentation we can have multiple BARs in our
xilinx-virtex6-FPGA card (page 74)
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact
=8&ved=0ahUKEwj9parJicLTAhUBPxQKHUzQAiUQFggqMAE&url=https%3A%2F%2Fwww.xilinx
.com%2Fsupport%2Fdocumentation%2Fuser_guides%2Fv6_pcie_ug517.pdf&usg=AFQjCNH
dRFVO5Us8BF48LgHn_qbE3vIn9A&sig2=54Zq4u71pyIPDVy-iOhKmg
what does it mean? does it mean i don’t need bus driver anymore?
thx alot for your help
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i found this text in one of xilinx documentation:
“The PCIe solution has the ability to operate as a multifunction device. This type of device has
several functions all sharing a single PCIe link. Each function has its own PCIe Configuration Header space; thus, from a host-system software perspective, each function appears as an individual PCIe
device on its own PCIe link. This greatly simplifies device driver development and portability because the driver developer can create a single driver and replicate it for each hardware function”
based on your introduced link, and the documentations on xilinx-PCIe endpoint, I conclude I don’t need bus driver. and this part of MSDN’s doc applied for my situation:
“The system supplied multifunction driver (mf.sys) can handle the bus-level enumeration and resource allocation requirements for the device, and the system-supplied INF (mf.sys) can install the multifunction device. You need to supply only a function driver and INF file for each of the individual device functions.”
am i right? should i just be worried about using mf.sys and a proper function driver?
thanks
You are correct, in fact if the sub-function looks exactly like a 16550 then
you will not need a driver at all, this should be detected by the system as
a standard serial port.
Don Burn
Windows Driver Consulting
Website: http://www.windrvr.com
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[mailto:xxxxx@lists.osr.com] On Behalf Of
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Sent: Saturday, April 29, 2017 3:38 AM
To: Windows System Software Devs Interest List
Subject: RE:[ntdev] UART in PCIE card
i found this text in one of xilinx documentation:
“The PCIe solution has the ability to operate as a multifunction device.
This type of device has several functions all sharing a single PCIe link.
Each function has its own PCIe Configuration Header space; thus, from a
host-system software perspective, each function appears as an individual
PCIe device on its own PCIe link. This greatly simplifies device driver
development and portability because the driver developer can create a single
driver and replicate it for each hardware function”
based on your introduced link, and the documentations on xilinx-PCIe
endpoint, I conclude I don’t need bus driver. and this part of MSDN’s doc
applied for my situation:
“The system supplied multifunction driver (mf.sys) can handle the bus-level
enumeration and resource allocation requirements for the device, and the
system-supplied INF (mf.sys) can install the multifunction device. You need
to supply only a function driver and INF file for each of the individual
device functions.”
am i right? should i just be worried about using mf.sys and a proper
function driver?
thanks
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> based on your introduced link, and the documentations on xilinx-PCIe endpoint, I
conclude I don’t need bus driver.
…
am i right? should i just be worried about using mf.sys and a proper function
driver?
If the device is multifunction in the genuine PCI sense (as in bus:device:function, and independent config. spaces for each function), the mf.sys is not used at all. The PCI driver will see each function as independent PCI device.
There will be a small performance hit with the interrupt handling. All functions share the (legacy line-based, level) interrupt line - so when one function raises the request, the ISR will be called for all functions, and the ISR must read some status register every time to find which function needs service. But the number of such functions is at most 8.
Regards,
– pa
thank you Pavel and Don.
as I explored more I found out probably using high-cost FPGA is not suitable for this project(ultraScale version of xilinx), so I better work on writing bus driver which seems more general.
if you have any advice or a place to start, I’ll appreciate 
> so I better work on writing bus driver which seems more general.
if you have any advice or a place to start, I’ll appreciate
See the first reply of Mr. Burn in this thread (Apr. 20) ?
– pa